1. Field of the Invention
The present invention relates to a semiconductor memory, and more specifically to a write control circuit for use in a synchronous semiconductor memory.
2. Description of Related Art
With a recent speed-up of microprocessors, a demand for elevating an access speed of a semiconductor memory is increasing. However, this demand has not yet been satisfied because of physical limits in micro-fabrication and an increased chip size attributable to an increased memory capacity. One of the approaches for realizing the speed-up of the semiconductor memory is a synchronous semiconductor memory having an internal pipeline structure, some examples of which have been disclosed by Japanese Patent Application Laid-open Publication JP-A-61-148692, JP-A-6-076566 which corresponds to U.S. Pat. No. 5,341,341, and Japanese Patent Application No. 232732/1994 which was laid open as JP-A-8-096573 on Apr. 12, 1996, which corresponds to EP-A-0704848 published on Apr. 3, 1996. The disclosure of these publications is incorporated by reference in their entirety into this application.
This synchronous semiconductor memory having the internal pipeline structure, is featured in that, at the time of reading, an address access path is divided into a plurality of stages, and the reading is carried out in a time-division manner, so that a cycle time is shortened. Therefore, at the time of writing, it is necessary to write data into a sense amplifier during the shortened cycle time.
Referring to FIG. 1, there is shown a block diagram illustrating one example of the prior art synchronous semiconductor memory.
An input section of the shown semiconductor memory includes a plurality of input circuits connected to receive a plurality of bits of an input address ADD. These input circuits are represented by only one input circuit 1 for simplification of drawing. The input section also includes a plurality of input circuits 2 to 5 connected to receive a plurality of control signals RASB, CASB, WEB and CSB, respectively, an input circuit 6 connected to receive an external clock CLK, and an input circuit 7 connected to receive data DQ from a data input/output terminal.
An internal circuit of the shown semiconductor memory includes a synchronous signal generating circuit 8 connected to an output of the input circuit 6 for generating a synchronous signal ICLK1, a delay DL3 receiving the synchronous signal ICLK1 for generating another synchronous signal ICLK1D by delaying the received synchronous signal ICLK1 by a predetermined constant time, a command decoder 9 connected to receive outputs of the input circuits 2 to 5, for generating a read enable signal REN and a write enable signal WEN in synchronism with the synchronous signal ICLK1, and a pipeline enabling circuit 10 receiving the read enable signal REN, the write enable signal WEN and a burst end signal BSTEND explained hereinafter, for generating a pipeline enable signal PEN.
The internal circuit of the shown semiconductor memory also includes a burst counter 11 receiving an output of the input circuit 1, the pipeline enable signal PEN and the synchronous signal ICLK1, for generating a plurality of internal address signals IADD, plate selection signals PSEL1 and the above mentioned burst end signal BSTEND, a column decoder 12A receiving the plurality of internal address signals IADD, and having outputs connected to a plurality of column selection lines YSW, a buffer 19 receiving the plate selection signals PSEL1 for outputting plate selection signals PSEL2, another buffer 20 receiving an output of the input circuit 7 for outputting a write data to a write bus WBUS1, a write pulse generating circuit 13 receiving the pipeline enable signal PEN, the write enable signal WEN and the synchronous signal ICLK1, for generating a write pulse WP, an AND gate AN receiving the plate selection signals PSEL2 and the write pulse WP, for generating a write switch signal WSW, a write buffer 14 receiving the write switch signal WSW and the write bus WBUS1, for supplying a write data to write bus pairs WBUS2T/N, an array of memory cells 15, and sense amplifiers 16 connected to the column selection lines YSW and the write bus pairs WBUS2T/N, and also connected to the memory cell array 15 through digit line pairs DT/N.
The write pulse generating circuit 13 includes a NAND gate NAN3 receiving the pipeline enable signal PEN, the write enable signal WEN and the synchronous signal ICLK1, a delay DL4 receiving an output of the NAND gate NAN3 for generating a signal by delaying the received signal by a predetermined constant time, and a NAND gate NAN4 receiving the output of the NAND gate NAN3 and an output of the delay DL4, for outputting the write pulse WP.
Now, operation of the shown system will be described with reference to FIG. 2, which is a timing chart illustrating an operation of the prior art synchronous semiconductor memory.
If the control signals RASB, CASB, WEB and CSB are set to take respective levels indicative of a write command at a rising of the external clock CLK of a cycle C1, the command decoder 9 brings the write enable signal WEN to a high level in response to the synchronous signal ICLK1 which assumes a high level in response to the external clock CLK. Accordingly, the pipeline enable signal PEN is also brought to the high level by the pipeline enable circuit 10.
If the write command is inputted, the burst counter 11 generates an internal address IADD for a separately set "burst length". Here, the "burst length" means the number of bits of data to be written when one write command is applied, and is set at a time earlier than the cycle C1 in FIG. 2. The shown example illustrate the case that it is set to the "burst length"=2.
Therefore, the internal address IADD for the separately set "burst length" (2 bits) is generated in cycles C1 nd C2 by the burst counter 11, and then, a high level pulse is generated as the burst end signal BSTEND by the burst counter 11 in response to a rising of the synchronous signal ICLK1 of a cycle C3. In response to the burst end signal BSTEND, the pipeline enable circuit 10 brings the pipeline enable signal PEN to a low level.
In synchronism with the synchronous signal ICLK1, the plate selection signal PSEL1 and the internal address IADD (not shown in FIG. 2) are generated and the column decoder 12A receiving the internal address IADD selects one of the column selection lines YSW. In the shown example, the plate selection signals PSEL1 are not changed in the cycle C2, but the selected line of the column selection lines YSW is changed for each cycle. In addition, the content of the plate selection signals PSEL1 are transferred as the plate selection signals PSEL2, and a write data is transferred to the write bus WBUS1.
During the cycle C1, after both the write enable signal WEN and the pipeline enable signal PEN are brought to the high level, if the synchronous signal ICLK1D is generated with the predetermined constant delay time from the synchronous signal ICLK1, the output of the NAND gate NAN3 is brought to a low level (this is not shown in FIG. 2), and therefore, the write pulse WP is brought to a high level. Thereafter, if the synchronous signal ICLK1D is brought to the low level, the output of the delay DL4 is brought to the high level after the predetermined delay time (this is also not shown in FIG. 2), with the result that the write pulse WP is brought to the low level.
During the next cycle C2, the write pulse WP is similarly generated, but during the cycle C3, the write pulse WP is maintained at the low level, because the pipeline enable signal PEN is brought to the low level before the synchronous signal ICLK1D is brought to the high level, and therefore, the output of the NAND gate NAN3 remains at the high level. On the other hand, the write data is transferred to the write bus pairs WBUS2T/N when the write switch signal WSW (which is generated in response to the write pulse WP during a period that the plate selection signal PSEL2 is at the high level) is at the high level.
Here, it is sufficient if the rising timing of the synchronous signal ICLK1D is determined by adjusting the delay amount of the delay DL3 to the effect that the write switch signal WSW is brought to the high level after the column selection lines YSW, the plate selection signals PSEL2 and the write bus WBUS1 are changed, and if the delay amount of the delay DL4 is adjusted to ensure that the write switch signal WSW is brought to the low level after data has been accurately written into the sense amplifier 16.
As seen from the above, the write execution time, namely, the high level width of the write pulse WP is determined by the delay amount of the delay DL4. Assuming that the write execution time is t.sub.WP and the cycle time is t.sub.CK, the low level width t.sub.WPB of the write switch signal WSW is expressed as follows: EQU t.sub.WPB =t.sub.CK -t.sub.WP ( 1)
In addition, assuming that a minimum value of the low level width t.sub.WPB of the write pulse WP and the write switch signal WSW, required for changing the column selection lines YSW, the plate selection signals PSEL2 and the write bus WBUS1, is t.sub.WPBmin, the cycle time t.sub.CK is expressed as follows: EQU t.sub.CK &gt;t.sub.WP +t.sub.WPBmin ( 2)
Referring to FIG. 3, there is shown a timing chart illustrating an operation of the prior art synchronous semiconductor memory in the case that the cycle time t.sub.CK is long. As seen from comparison between FIGS. 2 and 3, even if the cycle time t.sub.CK is long, the write execution time t.sub.WP is the same as that of the example shown in FIG. 2. Namely, the write execution time t.sub.WP is constant independently of the cycle time t.sub.CK.
The required write execution time t.sub.WP is different from one semiconductor memory to another, because of a manufacturing process variation. Accordingly, it is necessary to determine the delay amount of the delay DL4 and to set the write execution time t.sub.WP, with a margin which makes it possible to perform an accurate writing in most of devices.
In other words, the write execution time t.sub.WP is set to meet with devices manufactured under the process condition which needs the longest write execution time, by taking the manufacturing process variation into consideration. As a result, in devices manufactured under a standard process condition, the write execution time t.sub.WP becomes longer than a required time, which results in an unnecessarily long cycle time t.sub.CK. Namely, all of devices have the same long cycle time t.sub.CK as that of the devices manufactured under the process condition which needs the longest write execution time.
At present, the cycle time for the reading is being speeded up, and therefore, the speed grade is often determined by the cycle time for the writing. In the above mentioned situation, only devices having a low speed grade can be manufactured.
If the write execution time t.sub.WP is set to meet with the devices manufactured under the standard process condition, the number of devices which cannot accurately write and therefore become defective, increases.
Under the above mentioned circumstance, in order to shorten the cycle time for the writing, Japanese Patent Application Laid-open Publication JP-A-4-243085, which corresponds to U.S. Pat. No. 5,293,347, proposes to provide two write buffers or drivers for one sense amplifier. The disclosure of these publications is incorporated by reference in their entirety into this application.
However, in this approach, the write execution time required for one writing cannot be shortened, and therefore, it was still necessary to set the write execution time t.sub.WP so as to meet with devices manufactured under the process condition which needs the longest write execution time.